Computer Science 552:
Asynchronous VLSI Design (3.0 units)
Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
- Prerequisite: EE 477
- Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
- Crosslist: This course is offered by the EE department but may qualify for major credit in CSCI. To register, enroll in EE 552.
| Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
|---|---|---|---|---|---|---|---|---|---|
| 30624D | 048 | Lecture | 6:30-9:20pm | Monday | 14 of 40 | Recep Ozdag | OHE136 |   | |
| 30625R | 048 | Discussion | 3:00-3:50pm | Friday | 14 of 40 | OHE100B | | ||
| 30622D | 034 | Lecture | 6:30-9:20pm | Monday | 9 of 15 | Recep Ozdag | OFF CAMPUS |  | |
| 30623R | 034 | Discussion | 3:00-3:50pm | Friday | 9 of 20 | OFF CAMPUS | |