Electrical Engineering 552:

Asynchronous VLSI Design (3.0 units)

Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
  • Prerequisite: EE 477
  • Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
30624D048Lecture6:30-9:20pmMonday14 of 40Recep OzdagOHE136feesession dates
30625R048Discussion3:00-3:50pmFriday14 of 40OHE100Bsession dates
30622D034Lecture6:30-9:20pmMonday9 of 15Recep OzdagOFF CAMPUSnotefeesession dates
30623R034Discussion3:00-3:50pmFriday9 of 20OFF CAMPUSsession dates
Information accurate as of March 14, 2008 4:46 am.
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