Electrical and Computer Engineering 560L:
Digital System Design (4.0 units)
Hardware System Design and implementation, FPGAs, HDL design, timing, FIFOs, Cache, CAMs, SSRAMs, OoO/multi-threaded CPU design, cache coherency, clock-domain crossing, bus protocols. Prerequisite: EE 457.
- Prerequisite: EE 457
| Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
|---|---|---|---|---|---|---|---|---|---|
| 30460D | 179 | Lecture | 1:00-4:40pm | Tue, Thu | 42 of 42 | Mark Redekopp | OHE100C |  | |
| 30462D | 190 | Lecture | 1:00-4:40pm | Tue, Thu | 7 of 10 | Mark Redekopp | DEN@Viterbi | | |
| 30461R | 179 | Lab | 1:30-3:30pm | Friday | 5 of 30 | SSL202 | | ||
| 30463R | 179 | Lab | 3:00-5:00pm | Wednesday | 38 of 45 | OHE100C | | ||
| 30464D | 190 | Lab | 3:00-5:00pm | Wednesday | 6 of 10 | DEN@Viterbi | |