Electrical and Computer Engineering 552:
Asynchronous VLSI Design (4.0 units)
Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous, locally synchronous design.
- Prerequisite: EE 477
- Restriction: Registration open to the following class level(s): Doctoral Student, Master Student
- Note: Register for lecture and discussion
| Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
|---|---|---|---|---|---|---|---|---|---|
| 30702R | 048 | Lecture | 9:00-10:50am | Tue, Thu | 53 of 82 | Peter Beerel | OHE132 | PDF (483600 KB) |   |
| 30703R | 048 | Discussion | 1:00-1:50pm | Friday | 53 of 82 | OHE122 | | ||
| 30700D | 034 | Lecture | 9:00-10:50am | Tue, Thu | 4 of 20 | Peter Beerel | DEN@Viterbi | | |
| 30701R | 034 | Discussion | 1:00-1:50pm | Friday | 4 of 20 | DEN@Viterbi | |