Electrical Engineering 552:

Asynchronous VLSI Design (3.0 units)

Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
  • Prerequisite: EE 477
  • Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
  • Note: Register for lecture and discussion
30702D048Lecture6:40-9:20pmTuesday13 of 45Dan Gunnar Mika NystroemRTH105notefeesession dates
30703R048Discussion12:00-12:50pmFriday13 of 56OHE100Dsession dates
30700D034Lecture6:40-9:20pmTuesday1 of 20Dan Gunnar Mika NystroemDEN@Viterbinotefeesession dates
30701R034Discussion12:00-12:50pmFriday1 of 20DEN@Viterbisession dates
Information accurate as of October 3, 2018 10:51 am.