Electrical Engineering 552:
Asynchronous VLSI Design (3.0 units)
Asynchronous channels and architectures; implementation design styles; controller synthesis; hazards, and races; Petri-nets; performance analysis, and optimization; globally asynchronous locally synchronous design. Open only to graduate students.
- Prerequisite: EE 477
- Restriction: Registration open to the following class level(s): Master Student, Doctoral Student
- Note: Register for lecture and discussion
| Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
|---|---|---|---|---|---|---|---|---|---|
| 30702D | 048 | Lecture | 11:00-12:20pm | Tue, Thu | 36 of 50 | Peter Beerel | OHE100D |    | |
| 30703R | 048 | Discussion | 12:00-12:50pm | Friday | 36 of 50 | OHE100D | | ||
| 30700D | 034 | Lecture | 11:00-12:20pm | Tue, Thu | 3 of 20 | Peter Beerel | DEN@Viterbi | | |
| 30701R | 034 | Discussion | 12:00-12:50pm | Friday | 3 of 20 | DEN@Viterbi | | ||
| 30665D | 048 | Lecture | 5:00-7:50pm | Monday | Canceled | | |||
| 30449R | 048 | Discussion | 5:00-5:50pm | Thursday | Canceled | |