Electrical Engineering 201L:
Introduction to Digital Circuits (4.0 units)
Digital system design and implementation; synchronous design of datapath and control; schematic/Verilog-based design, simulation, and implementation in Field Programmable Gate Arrays; timing analysis; simple CPU design; semester-end project. Prerequisite: EE-101.
- Prerequisite: EE 101
- Note: Register for one lecture, lab and quiz
Section | Session | Type | Time | Days | Registered | Instructor | Location | Syllabus | Info |
---|---|---|---|---|---|---|---|---|---|
30416R | 001 | Lecture | 2:00-3:20pm | Tue, Thu | 46 of 50 | Gandhi Puvvada | RTH105 | ![]() ![]() ![]() | |
30420R | 001 | Lecture | 10:30-11:50am | Mon, Wed | 50 of 51 | Gandhi Puvvada | RTH105 | ![]() ![]() | |
30978R | 001 | Discussion | TBA | TBA | 6 of 20 | OFFICE | ![]() | ||
30440R | 001 | Quiz | 4:00-6:00pm | Friday | 91 of 180 | TBA | ![]() | ||
30434R | 001 | Lab | 6:00-8:50pm | Monday | 20 of 20 | OHE336 | ![]() | ||
30436R | 001 | Lab | 5:00-7:50pm | Wednesday | 19 of 20 | OHE336 | ![]() | ||
30438R | 001 | Lab | 5:00-7:50pm | Tuesday | 21 of 20 | OHE336 | ![]() | ||
30976R | 001 | Lab | 5:00-7:50pm | Thursday | 19 of 20 | OHE336 | ![]() | ||
30979R | 001 | Lab | 1:00-3:30pm | Friday | 17 of 22 | OHE336 | ![]() |